The present invention relates to a serial access memory and, more particularly, to an asynchronous serial access memory formed of a large-capacity DRAM used in a television set or the like.
A serial access memory employed in a television, a VCR, or the like has an independent input terminal and an independent output terminal, enabling an input clock and an output clock to have entirely different frequencies. This type of asynchronous serial access memory permits simultaneous access to input and output, so that it finds a variety of applications. For example, such an asynchronous serial access memory is used in an application where images recorded on a video tape by a video camera is viewed on a television screen by using a VCR.
In this case, to videotape images using a video camera, a synchronization clock CLK1 of a video camera system. However, when the video tape is set in a VCR for playback, a timing clock is an asymmetric waveform clock due to stretching of the tape or a mechanical operation of a VCR servo system rather than the synchronization clock CLK1 for reading video data from the video tape.
Image data synchronized with the asymmetric waveform clock cannot be subjected to image processing by the VCR, thus requiring conversion into image data synchronized with a shaped synchronization clock CLK2 in the VCR system. For this purpose, the asynchronous serial access memory is used because it enables writing to be accomplished using an asymmetric waveform clock and reading to be accomplished using a shaped clock.
In another example, the asynchronous serial access memory is used to transfer data on a personal computer screen to a television, an LCD panel, or the like. The graphic drawing frequency of the personal computer screen is different from that of the television; therefore, the graphic drawing frequency must be changed to bring the data displayed on the personal computer screen onto the television screen. This is efficiently achieved by using the asynchronous serial access memory because allows input to be performed at the graphic drawing frequency of the personal computer and output to be performed at the frequency of the television.
This type of asynchronous serial access memory has, as its data storage area, a DRAM array that has a large capacity of 2 Mbits or more and has many memory columns that are constituted by plurality of memory cells comprised of transistors and capacitors and are connected to a bit line. The asynchronous serial access memory is further provided with a write data bus for transferring entered data and a write data register that is connected to the write data bus and temporarily saves the entered data. The asynchronous serial access memory is further provided with a read data bus for transferring data to be output and a read data register that is connected to the read data bus and temporarily saves the data to be output.
Normally, the number of memory columns of the asynchronous serial access memory is equal to the number of pixels on a line constituting an image. A television screen with a large screen and a high resolution or a high-resolution LCD panel for a personal computer involves more pixel information on a unit line constituting a screen, requiring more memory columns. This results in a longer write data bus and a longer read data bus with a larger additional capacity. Furthermore, more write data registers and more read data registers are connected to the write data bus and the read data bus, respectively, leading to larger additional capacities of connection nodes. Hence, the increased load capacity causes a slower access.
The asynchronous serial access memory has the DRAM array that is fabricated with minimized bit line pitch and word line pitch for the necessity of achieving a larger capacity. In the asynchronous serial access memory, a write data register and a read data register must be connected for each pair of bit lines. However, the pitch for each pair of bit lines becomes too small to plot each data register pattern according to an applicable process rule, and it becomes necessary to increase the pitch for each pair of bit lines itself. This results in an excessively large chip area and higher cost than that of a typical DRAM.